VLSI

Digital design, RTL, verification, FPGA, mixed-signal — the tape-out culture, taught hands-on.

• Combinational and sequential logic in Verilog
• Testbenches and functional verification
• FPGA synthesis and timing closure
• Introduction to the ASIC tape-out flow

Taught by working VLSI engineers.

This page is a placeholder for the Goal 0 demo — enrolment and curriculum detail ship in a later phase.